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Radiation-Hardened FPGAs
Features
* * * * * * * * Guaranteed Total Dose Radiation Capability Low Single Event Upset Susceptibility High Dose Rate Survivability Latch-Up Immunity Guaranteed QML Qualified Devices Commercial Devices Available for Prototyping and Pre-Production Requirements Gate Capacities of 2,000 and 8,000 Gate Array Gates More Design Flexibility than Custom ASICs * * * * * * * * * * Significantly Greater Densities than Discrete Logic Devices Replaces up to 200 TTL Packages Design Library with over 500 Macro Functions Single-Module Sequential Functions Wide-Input Combinatorial Functions Up to Two High-Speed, Low-Skew Clock Networks Two In-Circuit Diagnostic Probe Pins Support Speed Analysis to 50 MHz Non-Volatile, User Programmable Devices Fabricated in 0.8 Epitaxial Bulk CMOS Process Unique In-System Diagnostic and Verification Capability with Silicon Explorer
Product Family Profile
Device Capacity System Gates Gate Array Equivalent Gates PLD Equivalent Gates TTL Equivalent Packages 20-Pin PAL Equivalent Packages Logic Modules S-Modules C-Modules Flip-Flops (Maximum) Routing Resources Horizontal Tracks/Channel Vertical Tracks/Channel PLICE Antifuse Elements User I/Os (Maximum) Packages (by Pin Count) Ceramic Quad Flat Pack (CQFP) RH1020 3,000 2,000 6,000 50 20 547 0 547 273 22 13 186,000 69 84 RH1280 12,000 8,000 20,000 200 80 1,232 624 608 998 35 15 750,000 140 172
April 2005 (c) 2005 Actel Corporation
i See the Actel website for the latest version of the datasheet.
Radiation-Hardened FPGAs
Ordering Information
RH1280 - CQ 172 V
Application V = QML Qualified Package Lead Count Package Type CQ = Ceramic Quad Flat Pack Part Number RH1280 = 8000 Gates RH1020 = 2000 Gates
Figure 1-1 * Ordering Information
Ceramic Device Resources
CQFP 84-Pin RH1020 RH1280 69 - CQFP 172-Pin - 140
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Table of Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Radiation Survivability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 QML Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 RadHard Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 The RH1020 Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 QML Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Radiation Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Sequential Module Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 84-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 172-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 International Traffic in Arms Regulations (ITAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
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Radiation-Hardened FPGAs
General Description
Actel Corporation, the leader in antifuse-based field programmable gate arrays (FPGAs), offers fully guaranteed RadHard versions of the A1280 and A1020 devices with gate densities of 8,000 and 2,000 gate array gates, respectively. The RH1020 and RH1280 devices are processed in 0.8 , two-level metal epitaxial bulk CMOS technology. The devices are based on the Actel patented channeled array architecture, and employ Actel's PLICE antifuse technology. This architecture offers gate array flexibility, high performance, and fast design implementation through user programming. Actel devices also provide unique on-chip diagnostic probe capabilities, allowing convenient testing and debugging. On-chip clock drivers with hard-wired distribution networks provide efficient clock distribution with minimum skew. A security fuse may be programmed to disable all further programming, and to protect the design from being copied or reverse engineered. The RH1020 and RH1280 are available as fully qualified QML devices. Unlike traditional ASIC devices, the design does not have to be finalized six months prior to receiving the devices. Customers can make design modifications and program new devices within hours. These devices are fabricated, assembled, and tested at the Lockheed-Martin Space and Electronics facility in Manassas, Virginia on an optimized radiation-hardened CMOS process. line by expensive and destructive testing. QML also ensures continuous process improvement, a focus on enhanced quality and reliability, and shortened product introduction and cycle time. Actel Corporation has also achieved QML certification. All RH1020 and RH1280 devices will be shipped with a "QML" marking, signifying that the devices and processes have been reviewed and approved by DESC for QML status.
Development Tool Support
The RadHard family of FPGAs is fully supported by both Actel Libero(R) Integrated Design Environment (IDE) and Designer FPGA development software. Actel Libero IDE is a design management environment, seamlessly integrating design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment. Libero IDE includes Synplify(R) for Actel from Synplicity(R), ViewDraw(R) for Actel from Mentor Graphics(R), ModelSim(R) HDL Simulator from Mentor Graphics, WaveFormer LiteTM from SynaptiCADTM, and Designer software from Actel. Refer to the Libero IDE flow diagram for more information (located on the Actel website). Actel Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes timing-driven place-and-route, and a world-class integrated static timing analyzer and constraints editor. With the Designer software, a user can select and lock package pins while only minimally impacting the results of place-and-route. Additionally, the back-annotation flow is compatible with all the major simulators and the simulation results can be cross-probed with Silicon Explorer II, Actel's integrated verification and logic analysis tool. Another tool included in the Designer software is the ACTgen macro builder, which easily creates popular and commonly used logic functions for implementation in your schematic or HDL design. Actel's Designer software is compatible with the most popular FPGA design entry and verification tools from companies such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems.
Radiation Survivability
In addition to all electrical limits, all radiation characteristics are tested and guaranteed, reducing overall system-level risks. With total dose hardness of 300 krad (Si), latch-up immunity, and a tested single event upset (SEU) of less than 1x10-6 errors/bit-day, these are the only RadHard, high-density field programmable products available today.
QML Qualification
Lockheed Martin Space and Electronics in Manassas, Virginia has achieved full QML certification, assuring that quality management, procedures, processes, and controls are in place from wafer fabrication through final test. QML qualification means that quality is built into the production process rather than verified at the end of the
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Radiation-Hardened FPGAs
Applications
The RH1020 and RH1280 devices are targeted for use in military and space applications subject to radiation effects. 1. Accumulated Total Dose Effects With the significant increase in Earth-orbiting satellite launches and the ever-decreasing time-tolaunch design cycles, the RH1020 and RH1280 devices offer the best combination of total dose radiation hardness and quick design implementation necessary for this increasingly competitive industry. In addition, the high total dose capability allows the use of these devices for deep space probes, which encounter other planetary bodies where the total dose radiation effects are more pronounced. 2. Single Event Effects (SEE) Many space applications are more concerned with the number of single event upsets and potential for latchup in space. The RH1020 and RH1280 devices are latch-up immune, guaranteeing that no latch-up failures will occur. Single event upsets can occur in these devices as with all semiconductor products, but the rate of upset is low, as shown in Table 1-2 on page 1-6. 3. High Dose Rate Survivability An additional radiation concern is high dose rate survivability. Solar flares and sudden nuclear events can cause immediate high levels of radiation. The RadHard devices are appropriate for use in these types of applications, including missile systems, ground-based communication systems, and orbiting satellites.
where
S0 = A0 x B0 S1 = A1 + B1
A0 B0 D00 D01 D10 D11 A1 B1
S0
Y
S1
Figure 1-1 * C-Module Implementation
The S-module, shown in Figure 1-2 on page 1-3, is designed to implement high-speed sequential functions within a single logic module. The S-module implements the same combinatorial logic function as the C-module while adding a sequential element. The sequential element can be configured as either a D-flip-flop or a transparent latch. To increase flexibility, the S-module register can be bypassed so it implements purely combinatorial logic. Flip-flops can also be created using two C-modules. The single event upset (SEU) characteristics differ between an S-module flip-flop and a flip-flop created using two C-modules. For details see the Radiation Specifications table on Table 1-2 on page 1-6 and the Design Techniques for RadHard Field Programmable Gate Arrays application note.
RadHard Architecture
The RH1020 and RH1280 architecture is composed of fine-grained building blocks that produce fast and efficient logic designs. All the devices are composed of logic modules, routing resources, clock networks, and I/O modules, which are the building blocks for fast logic designs.
The RH1020 Logic Module
The RH1020 logic module is an 8-input, one-output logic circuit chosen for the wide range of functions it implements and for its efficient use of interconnect routing resources (Figure 1-3 on page 1-3). The logic module can implement the four basic logic functions (NAND, AND, OR, and NOR) in gates of two, three, or four inputs. Each function may have many versions, with different combinations of active-low inputs. The logic module can also implement a variety of D-latches, exclusivity functions, AND-ORs, and OR-ANDs. No dedicated hardwired latches or flip-flops are required in the array, since latches and flip-flops may be constructed from logic modules wherever needed in the application.
Logic Modules
RH1280 devices contain two types of logic modules, combinatorial (C-modules) and sequential (S-modules). RH1020 devices contain only C-modules. The C-module, shown in Figure 1-1, implements the following function:
Y = !S1 x !S0 x D00 + !S1 x S0 x D01 + S1 x !S0 x D10 + S1 x S0 x D11 EQ 1-1
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D00 D01 D10 D11 S1
Y S0
D CLR
Q
OUT
D00 D01 D10 D11 S1
Y S0
D GATE
Q
OUT
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
Up to 7-Input Function Plus Latch
D00
D0 Y D1 S D GATE CLR Q OUT
D01 D10 D11 S1
Y S0
OUT
Up to 4-Input Function Plus Latch with Clear
Figure 1-2 * S-Module Implementation
Up to 8-Input Function (same as C-Module)
EN Q D PAD G/CLK*
From Array
To Array
Q
D
G/CLK*
Note: *Can be configured as a Latch or D Flip-Flop (using C-Module). Figure 1-4 * I/O Module
Figure 1-3 * RH1020 Logic Module
I/O Modules
I/O modules provide the interface between the device pins and the logic array. A variety of user functions, determined by a library macro selection, can be implemented in the I/O modules (refer to the Antifuse Macro Library Guide for more information). I/O modules contain a tristate buffer, and input and output latches which can be configured for input, output, or bidirectional pins (Figure 1-4).
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Radiation-Hardened FPGAs
RadHard devices contain flexible I/O structures in that each output pin has a dedicated output enable control. The I/O module can be used to latch input and/or output data, providing a fast set-up time. In addition, the Actel Designer software tools can build a D-flip-flop, using a C-module, to register input and/or output signals. Actel Designer development tools provide a design library of I/O macros that can implement all I/O configurations supported by the RadHard FPGAs.
Antifuse Structures
An antifuse is a "normally open" structure as opposed to the normally closed fuse structure used in PROMs or PALs. The use of antifuses to implement a programmable logic device results in highly testable structures, as well as efficient programming algorithms. The structure is highly testable because there are no pre-existing connections, enabling temporary connections to be made using pass transistors. These temporary connections can isolate individual antifuses to be programmed, as well as isolate individual circuit structures to be tested. This can be done both before and after programming. For example, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified.
Routing Structure
The RadHard device architecture uses vertical and horizontal routing tracks to interconnect the various logic and I/O modules. These routing tracks are metal interconnects that may either be of continuous length or broken into segments. Varying segment lengths allow over 90 percent of the circuit interconnects to be made with only two antifuse connections. Segments can be joined together at the ends, using antifuses to increase their length up to the full length of the track. All interconnects can be accomplished with a maximum of four antifuses.
Segmented Horizontal Routing Tracks
Logic Modules
Horizontal Routing
Horizontal channels are located between the rows of modules, and are composed of several routing tracks. The horizontal routing tracks within the channel are divided into one or more segments. The minimum horizontal segment length is the width of a module-pair, and the maximum horizontal segment length is the full length of the channel. Any segment that spans more than one-third the row length is considered a long horizontal segment. A typical channel is shown in Figure 1-5. Non-dedicated horizontal routing tracks are used to route signal nets. Dedicated routing tracks are used for the global clock networks and for power and ground tie-off tracks.
Antifuses
Vertical Routing Tracks
Figure 1-5 * Routing Structure
Related Documents
Application Notes
Design Techniques for RadHard Field Programmable Gate Arrays http://www.actel.com/documents/Des_Tech_RH_AN.pdf
Analysis of SDI/DCLK Issue for RH1020 and RT1020
Vertical Routing
Another set of routing tracks run vertically through the module. There are three types of vertical tracks, input, output, and long, that can be divided into one or more segments. Each segment in an input track is dedicated to the input of a particular module. Each segment in an output track is dedicated to the output of a particular module. Long segments are uncommitted and can be assigned during routing. Each output segment spans four channels (two above and two below), except near the top and bottom of the array where edge effects occur. Long vertical tracks contain either one or two segments. An example of vertical routing tracks and segments is shown in Figure 1-5.
http://www.actel.com/documents/SDI_DCLK_AN.pdf Simultaneously Switching Noise and Signal Integrity http://www.actel.com/documents/SSN_AN.pdf
User's Guides
Antifuse Macro Library Guide http://www.actel.com/documents/libguide_UG.pdf
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QML Flow
Test Inspection Wafer Lot Acceptance Serialization Die Adhesion Test Bond Pull Test Internal Visual Temperature Cycle Constant Acceleration Particle Impact Noise Detection (PIND) X-Ray Radiography Pre Burn-In Electrical Parameters (T0) Dynamic Burn-In Interim Electrical Parameters (T1) Percent Defective Allowable (PDA) Static Burn-In Final Electrical Parameters (T2) Percent Defective Allowable (PDA) Seal - Fine/Gross Leak External Visual (as required) Method LMFS Procedure MAN-STC-Q014 Required - 100% 2027 (Stud Pull) 2011 (Wirebond) 2010, Condition A 1010, Condition C, 50 Cycles 2001, Condition D or E, Y1 Orientation Only 2020, Condition A 2012 Per Device Specification 1015, 240 Hour Minimum, 125C Per Device Specification LMFS Procedure MAN-STC-Q016 1015, 144 Hour Minimum, 125C Minimum Per Device Specification LMFS Procedure MAN-STC-Q016 1014 2009
Absolute Maximum Ratings
Table 1-1 * Free Air Temperature Range Symbol VCC VI VO IIO TSTG Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. 2. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the recommended operating conditions. 3. VPP = VCC , except during device operation. 4. VSV = VCC , except during device operation. 5. VKS = GND , except during device operation. 6. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5 V or less than GND - 0.5V, the internal protection diode will be forward-biased and can draw excessive current. DC Supply Parameter Voltage2,3,4,5 Limits -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 Current6
2
Units V V V mA C
Input Voltage Output Voltage I/O Source/Sink
20 -65 to +150
Storage Temperature
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Radiation-Hardened FPGAs
Recommended Operating Conditions
Parameter Temperature Range1 Power Supply Tolerance Notes: 1. Case temperature (TC) is used. 2. All power supplies must be in the recommended operating range.
2
Military -55 to +125 10
Units C %VCC
Electrical Specifications
Symbol VOH1 VOL1 VIH VIL Input Transition Time CIO, I/O Capacitance2 IIH, IIL IOZL, IOZH ICC Standby3 Notes: 1. Only one output tested at a time. VCC = min. 2. Not tested, for information only. 3. All outputs unloaded. All inputs = VCC or GND. VIN = VCC or GND VCC = 5.5 V VOUT = VCC or GND VCC = 5.5 V tR, tF2 Test Conditions (IOH = -4 mA) (IOL = 4 mA) Group A Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 -- 4 1, 2, 3 1, 2, 3 1, 2, 3 -10 -10 2.2 -0.3 Limits Min. 3.7 0.4 VCC + 0.3 0.8 500 20 10 10 25 Max. Units V V V V ns pF A A mA
Radiation Specifications
Table 1-2 * Radiation Specifications1, 2 Symbol RTD SEL SEU1 SEU2
3 3
Characteristics Total Dose Single Event Latch-Up Single Event Upset for S-modules Single Event Upset for C-modules Single Event Fuse Rupture Neutron Fluence
Conditions
Min.
Max. 300 k
Units Rad (Si) Fails/Device-Day Upsets/Bit-Day Upsets/Bit-Day FIT (Fails/Device/1E9 Hrs) N/cm2
-55C Tcase 125C -55C Tcase 125C -55C Tcase 125C -55C Tcase 125C >1 E+12
0 1E-6 1E-7 <1
SEU33 RNF
Notes: 1. Measured at room temperature unless otherwise stated. 2. Device electrical characteristics are guaranteed for post-irradiation levels at worst-case conditions. 3. 10% worst-case particle environment, geosynchronous orbit, 0.025" of aluminum shielding. Specification set using the CREME code upset rate calculation method with a 2 epi thickness.
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Package Thermal Characteristics
The device junction to case thermal characteristics is jc, and the junction to ambient air characteristics is ja. The thermal characteristics for ja are listed with two different air flow rates, as shown in Table 1-3. Maximum junction temperature is 150C. A sample calculation of the maximum power dissipation for an 84-pin ceramic quad flat pack at commercial temperature is shown in EQ 1-2.
Max. Junction Temperature ( C ) - Max. Commercial Temperature ( C ) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- = 150C - 70C = 2.0 W -----------------------------------40C/W ja (C/W) EQ 1-2 Table 1-3 * Thermal Characteristics ja Package Type Ceramic Quad Flat Pack Ceramic Quad Flat Pack Pin Count 84 172 jc 2.0 2.0 Still Air 40.0 28.0 1.0 m/s 200 ft. / min. 33.0 23.1 2.5 m/s 500 ft. / min. 30.0 21.0 Units C/W C/W
Note: jc for CQFP packages refers to the thermal resistance between the junction and the bottom of the package.
Power Dissipation
General Power Equation
P = [ICCstandby + ICCactive] x VCC + IOL x VOL x N + IOH x (VCC - VOH) x M EQ 1-3
greater reduction in board-level power dissipation can be achieved. The power due to standby current is typically a small component of the overall power. Standby power is calculated below for military, worst case conditions. ICC 1 mA VCC 5.5 V Power 138 mW (max) 5.5 mW (typ) 25 mA 5.5 V
where ICCstandby is the current flowing when no inputs or outputs are changing. ICCactive is the current flowing due to CMOS switching. IOL, IOH are TTL sink/source currents. VOL, VOH are TTL level output voltages. N equals the number of outputs driving TTL loads to VOL. M equals the number of outputs driving TTL loads to VOH. Accurate values for N and M are difficult to determine because they depend on the family type, design details, and on the system I/O. The power can be divided into two components: static and active.
Active Power Components
Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency-dependent and a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs. An additional component of the active power dissipation is the totempole current in CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. The power dissipated by a CMOS circuit can be expressed by EQ 1-4:
Power (uW) = CEQ x VCC2 x F EQ 1-4
Static Power Components
Actel FPGAs have small static power components that result in lower power dissipation than PALs or PLDs. By integrating multiple PALs/PLDs into one FPGA, an even
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Radiation-Hardened FPGAs
where CEQ VCC F = Equivalent capacitance in pF = Power supply in volts (V) = Switching frequency in MHz
Equivalent Capacitance
Equivalent capacitance is calculated by measuring ICC active at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency-independent so the results may be used over a wide range of operating conditions. Equivalent capacitance values follow.
CEQCR = Equivalent capacitance of routed array clock in pF CL = Output lead capacitance in pF fm = Average logic module switching rate in MHz fn = Average input buffer switching rate in MHz = Average output buffer switching rate in MHz fp = Average first routed array clock rate in MHz fq1 fq2 = Average second routed array clock rate in MHz (RH1280 only)
Fixed Capacitance Values for Actel FPGAs (pF)
Device Type r1 routed_Clk1 69 168 r2 routed_Clk2 N/A 168
CEQ Values for Actel FPGAs
RH1020 RH1280 Modules (CEQM) Input Buffers (CEQI) Output Buffers (CEQO)
Routed Array Clock Buffer Loads (CEQCR)
RH1020 RH1280
3.7 22.1 31.2
4.6
5.2
11.6 23.8
3.5
Determining Average Switching Frequency
To determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. The following guidelines are meant to represent worst-case scenarios, so they can be generally used to predict the upper limits of power dissipation. These guidelines are as follow: Logic Modules (m) Inputs Switching (n) Outputs Switching (p) = 80% of Modules = # Inputs/4 = # Outputs/4
To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. EQ 1-5 shows a piece-wise linear summation over all components.
Power = VCC2 x [(m x CEQM x fm)modules + (n x CEQI x fn)inputs + (p x (CEQO+ CL) x fp)outputs + 0.5 x (q1 x CEQCR x fq1)routed_Clk1 + (r1 x fq1)routed_Clk1 + 0.5 x (q2 x CEQCR x fq2)routed_Clk2 + (r2 x fq2)routed_Clk2] EQ 1-5
First Routed Array Clock Loads = 40% of (q1) Sequential Modules Second Routed Array Clock Loads = 40% of Sequential (q2) (RH1280 only) Modules Load Capacitance (CL) = 35 pF Average Logic Module Switching = F/10 Rate (fm) Average Input Switching Rate = F/5 (fn) Average Output Switching Rate = F/10 (fp) Average First Routed Array Clock = F Rate (fq1) Average Second Routed Array = F/2 Clock Rate (fq2) (RH1280 only)
where m n p q1 q2 r1 r2 = = = = = = = Number of logic modules switching at fm Number of input buffers switching at fn Number of output buffers switching at fp Number of clock loads on the first routed array clock Number of clock loads on the second routed array clock (RH1280 only) Fixed capacitance due to first routed array clock Fixed capacitance due to second routed array clock (RH1280 only) Equivalent capacitance of logic modules in pF Equivalent capacitance of input buffers in pF Equivalent capacitance of output buffers in pF
CEQM = CEQI = CEQO =
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Timing Models
Input Delay I/O Module tINYL = 4.2 ns Internal Delays Logic Module Predicted Routing Delays Output Delay I/O Module
tIRD2 = 1.9 ns
tIRD1 = 1.2 ns tIRD4 = 4.2 ns tIRD8 = 8.9 ns
tPD = 3.9 ns tCO = 3.9 ns
tRD1 = 1.2 ns tRD2 = 1.9 ns tRD4 = 4.2 ns tRD8 = 8.9 ns
tDLH = 9.1 ns tENHZ = 13.5 ns
ARRAY CLOCK
tCKH = 7.6 ns FMAX = 55 MHz
FO = 128
Figure 1-6 * RH1020 Timing Model
Input Delays I/O Module tINYL = 2.3 ns tIRD2 = 7.5 ns Internal Delays Combinatorial Logic Module Predicted Routing Delays Output Delays I/O Module
tDLH = 8.7 ns D Q tPD = 4.7 ns tRD1 = 2.7 ns tRH2 = 3.4 ns tRD4 = 4.8 ns tRD8 = 9.0 ns
G t INH = 0.0 ns t INSU = 0.6 ns t INGL = 5.3 ns Sequential Logic Module
I/O Module tDLH = 8.7 ns
Combinatorial Logic included in tSUD
D
Q tRD1 = 2.7 ns
D
Q tENHZ = 9.7 ns
G tOUTH = 0.0 ns tOUTSU = 0.6 ns tGLH = 7.6 ns
ARRAY CLOCKS
tSUD = 0.7 ns tHD = 0.0 ns tCKH = 11.2 ns FMAX = 95 MHz FO = 384
tCO = 4.7 ns
tLCO = 17.7 ns (64 loads, pad-pad)
Note: Input module predicted routing delay. Figure 1-7 * RH1280 Timing Model
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Radiation-Hardened FPGAs
Parameter Measurement
Output Buffer Delays
E D TRIBUFF PAD To AC Test Loads (shown below)
In PAD VOL
50%
50% VOH 1.5V
E 1.5V tDHL PAD
50% V
50% 1.5V VOL 10% tENLZ
E PAD GND
50%
50% VOH 1.5V tENHZ
90%
tDLH
tENZL
tENZH
Figure 1-8 * Output Buffer Delays
AC Test Loads
Load 1 (Used to Measure Propagation Delay) Load 2 (Used to Measure Rising/Falling Edges) VCC GND
To the Output Under Test
35 pF To the Output Under Test
R to VCC for tPLZ / tPZL R to GND for tPHZ / tPZH R = 1 k
35 pF
Figure 1-9 * AC Test Loads
Input Buffer Delays
S A B PAD INBUF Y S, A or B Y 3V PAD Y GND tINYH 1.5V 1.5V VC C 50% tINYL 0V 50% Y tPLH 50% tPHL 50% 50% 50% tPHL 50% tPLH 50% Y
Figure 1-11 * Module Delays
Figure 1-10 * Input Buffer Delays
Module Delays
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Sequential Module Timing Characteristics
Flip-Flops and Latches
D E CLK
PRE CLR
Y
(Positive Edge Triggered)
tHD D1 tSUD G, CLK tSUENA t H EN A E tC O Q tR S PRE, CLR tWASYN t WCLKI tWC LKA tA
Note: D represents all data functions involving A, B, and S for multiplexed flip-flops. Figure 1-12 * Flip-Flops and Latches
DATA
PAD G
IBDL
CLK
PAD CLKBUF
DATA tINH G tINSU tH EXT CLK tSU EXT
Figure 1-13 * Input Buffer Latches
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Radiation-Hardened FPGAs
D OBDLHS G
PAD
D tOUTSU G tOUTH
Figure 1-14 * Output Buffer Latches
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Radiation-Hardened FPGAs
Timing Characteristics
Table 1-4 * RH1020 Timing Characteristics (Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125C, RTD = 300 krad (Si)) Parameter Description Min. Max. Units Logic Module Propagation Delays tPD1 tPD2 tCO tGO tRS Single Module Dual Module Macros Sequential Clk to Q Latch G to Q Flip-Flop (Latch) Reset to Q Delays1 1.2 1.9 2.8 4.2 8.9 ns ns ns ns ns 3.9 9.2 3.9 3.9 3.9 ns ns ns ns ns
Logic Module Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
2
Logic Module Sequential Timing tSUD tHD tSUENA tHENA tWCLKA tWASYN tA fMAX
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency
7.5 0.0 7.5 0.0 9.2 9.2 19.2 50
ns ns ns ns ns ns ns MHz
Input Module Propagation Delays tINYH tINYL Pad to Y High Pad to Y Low Delays1, 3 1.2 1.9 2.8 4.2 8.9 ns ns ns ns ns 4.2 4.2 ns ns
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 Notes:
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the DirectTime Analyzer utility. 3. Optimization techniques may further reduce delays by 0 to 4 ns. 4. The hold time for the DFME1A macro may be greater than 0 ns. Use the Designer v3.0 (or later) Timer to check the hold time for this macro.
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Radiation-Hardened FPGAs
Table 1-5 * RH1020 Timing Characteristics (Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125C, RTD = 300 krad (Si)) Parameter Description Min. Max. Units
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tP fMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 17.9 19.2 55 50 8.8 9.2 1.6 2.4 1.6 2.5 6.6 7.6 8.7 9.5 ns ns ns ns ns ns MHz
TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z Delta Low to High Delta High to Low 9.1 10.2 8.9 10.7 13.5 12.2 0.08 0.11 ns ns ns ns ns ns ns/pF ns/pF
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the Simultaneously Switching Noise and Signal Integrity application note. Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z Delta Low to High Delta High to Low 10.7 8.7 8.1 11.2 13.5 12.2 0.14 0.08 ns ns ns ns ns ns ns/pF ns/pF
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Table 1-6 * RH1280 Timing Characteristics (Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125C, RTD = 300 krad (Si)) Parameter Description
1
Min.
Max.
Units
Logic Module Propagation Delays tPD1 tCO tGO tRS Single Module
4.7 4.7 4.7 4.7
ns ns ns ns
Sequential Clk to Q Latch G to Q Flip-Flop (Latch) Reset to Q
2
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
3, 4
2.7 3.4 4.1 4.8 9.0
ns ns ns ns ns
Sequential Timing Characteristics tSUD tHD tSUENA tHENA tWCLKA tWASYN tA tINH tINSU tOUTH tOUTSU fMAX Notes:
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency
0.7 0.0 1.4 0.0 6.6 6.6 13.5 0.0 0.6 0.0 0.6 95
ns ns ns ns ns ns ns ns ns ns ns MHz
1. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal set-up (hold) time.
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Radiation-Hardened FPGAs
Table 1-7 * RH1280 Timing Characteristics (Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125C, RTD = 300 krad (Si)) Parameter Description Min. Max. Units
Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad to Y High Pad to Y Low G to Y High G to Y Low 1.9 2.3 4.1 5.3 ns ns ns ns
Input Module Predicted Routing Delays* tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period Maximum Frequency FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 0.0 0.0 4.6 5.8 11.8 13.0 105 95 5.8 6.2 5.8 6.2 1.1 1.1 9.6 11.2 9.6 11.2 ns ns ns ns ns ns ns ns MHz FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 6.8 7.5 8.2 8.9 11.7 ns ns ns ns ns
Note: *Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce delays by 0 to 4 ns.
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Radiation-Hardened FPGAs
Table 1-8 * RH1280 Timing Characteristics (Worst-Case Military Conditions, V CC = 4.5 V, T J = 1 25C, RT D = 30 0 krad (S i)) Parameter Description
1
Min.
Max.
Units
TTL Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL
Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z G to Pad High G to Pad Low I/O Latch Clock-Out (Pad-to-Pad), 64 Clock Loading Array Clock-Out (Pad-to-Pad), 64 Clock Loading Capacitive Loading, Low to High Capacitive Loading, High to Low
1
6.8 7.6 6.8 7.6 9.7 9.7 7.6 8.9 17.7 25.0 0.07 0.09
ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF
CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Notes:
Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z G to Pad High G to Pad Low I/O Latch Clock-Out (Pad-to-Pad), 64 Clock Loading Array Clock-Out (Pad-to-Pad), 64 Clock Loading Capacitive Loading, Low to High Capacitive Loading, High to Low
8.7 6.4 6.8 7.6 9.7 9.7 7.6 8.9 20.1 29.5 0.09 0.08
ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF
1. Delays based on 35 pF loading. 2. SSO information can be found in the Simultaneously Switching Noise and Signal Integrity application note.
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Radiation-Hardened FPGAs
Pin Description
CLKA Clock A (Input) NC No Connection
TTL clock input for clock distribution networks. The clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O.
CLKB Clock B (Input)
This pin is not connected to circuitry within the device.
PRA, I/O Probe A (Output)
Not applicable for RH1020. TTL clock input for clock distribution networks. The clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O.
DCLK1 Diagnostic Clock (Input)
TTL clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. If the Program fuse is not programmed and DCLK is undefined, it is configured as an inactive input. In this case, tie the DCLK pin to ground. If the Program fuse is programmed and DCLK is undefined, it will become an active LOW output.The Program fuse must be programmed if the DCLK pin is used as an output or a bidirectional pin.
GND Ground
The Probe A pin is used to output data from any userdefined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when verification has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. PRA is accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW.
PRB, I/O Probe B (Output)
LOW supply voltage.
I/O Input/Output (Input, Output)
The Probe B pin is used to output data from any userdefined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when verification has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. PRB is accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW.
SDI1 Serial Data Input (Input)
The I/O pin functions as an input, output, three-state, or bidirectional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Unused I/O pins are automatically driven LOW by the Designer software.
MODE Mode (Input)
The MODE pin controls the use of multi-function pins (DCLK, PRA, PRB, SDI). When the MODE pin is HIGH, the special functions are active. When the MODE pin is LOW, the pins function as I/Os. To provide debugging capability, the MODE pin should be terminated to GND through a 10 k resistor so that the MODE pin can be pulled HIGH when required.
Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. If the Program fuse is not programmed and SDI is undefined, it is configured as an inactive input. In this case, tie the SDI pin to ground. If the Program fuse is programmed and SDI is undefined, it will become an active LOW output.The Program fuse must be programmed if the SDI pin is used as an output or a bidirectional pin.
VCC 5.0V Supply Voltage
HIGH supply voltage.
1. Please refer to the Actel Technical Brief Analysis of SDI/DCLK Issue for RH1020 and RT1020.
1 -1 8
v3.1
Radiation-Hardened FPGAs
Package Pin Assignments
84-Pin CQFP
Pin #1 Index
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
84-Pin CQFP
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Figure 2-1 * 84-Pin CQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html.
v3.1
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Radiation-Hardened FPGAs
84-Pin CQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 RH1020 Function NC I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O VCC VCC I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC
84-Pin CQFP Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 RH1020 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O CLKA, I/O I/O MODE VCC VCC I/O I/O I/O SDI, I/O DCLK, I/O PRA, I/O PRB, I/O I/O I/O I/O I/O I/O I/O
84-Pin CQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 RH1020 Function GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O
2 -2
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Radiation-Hardened FPGAs
172-Pin CQFP
172 171 170 169 168 167 166 165 164 137 136 135 134 133 132 131 130
Pin #1 Index
1 2 3 4 5 6 7 8
129 128 127 126 125 124 123 122
172-Pin CQFP
35 36 37 38 39 40 41 42 43 95 94 93 92 91 90 89 88 87
44 45 46 47 48 49 50 51 52
79 80 81 82 83 84 85 86
Figure 2-2 * 172-Pin CQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html.
v3.1
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Radiation-Hardened FPGAs
172-Pin CQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 RH1280A Function MODE I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCC VCC I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O
172-Pin CQFP Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 RH1280A Function I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O
172-Pin CQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 RH1280A Function I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O
172-Pin CQFP Pin Number 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 RH1280A Function GND VCC GND VCC VCC I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O SDI, I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O
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Radiation-Hardened FPGAs
172-Pin CQFP Pin Number 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 RH1280A Function GND I/O I/O I/O I/O I/O I/O PRA, I/O I/O CLKA, I/O VCC GND I/O CLKB, I/O I/O PRB, I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O DCLK, I/O I/O
v3.1
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Radiation-Hardened FPGAs
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version Changes in Current Version (v3 . 1) v3.0 "Development Tool Support" section was updated. Table 1-1 was updated. Table 1-2 was updated. Table 1-3 was updated. The "DCLK Diagnostic Clock (Input)" section was updated. The "SDI1 Serial Data Input (Input)" section was updated. Page 1-1 1-5 1-6 1-7 1-18 1-18
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet Supplement." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advanced or production) containing general product information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families.
International Traffic in Arms Regulations (ITAR)
The product described in this datasheet are subject to the International Traffic in Arms Regulations (ITAR). They require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States.
v3.1
3-1
Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners.
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